Although metal oxide semiconductor field effect transistors (MOSFETs) are fabricated within a common silicon substrate, they must nevertheless be electrically isolated from one another. They can subsequently be interconnected to create specific circuit configurations.
MOSFETs are said to be "self isolated," i.e., as long as their source-substrate and drain-substrate pn junctions are held at reverse bias, drain current is due only to current flow from source to drain through a channel under the gate. However, the metal strips used to interconnect MOS transistors form gates of parasitic MOS transistors, with the oxide beneath them forming a gate oxide. To isolate MOSFETs, therefore, it is necessary to prevent the formation of channels in the field regions. One way to accomplish this is to utilize a comparatively thick field oxide layer. However as device dimensions shrink, the nature of the field oxide formation process hampers creation of smaller, isolated devices.
Using "isolation trenches" rather than relying completely on field oxidation allows higher integration while still isolating adjacent devices. Electronic devices, typically FETs, are formed on "mesas" which are separated by oxide-filled "trenches". FIGS. 1-7 show the typical prior art steps in creating oxide trenches, and the resulting structure.
As shown in FIG. 1, a first oxide layer 10, commonly referred to as a pad oxide layer, is provided on top of a silicon substrate 12. A nitride layer 14 is subsequently applied over pad oxide layer 10. Pad oxide layer 10 cushions the transition of stresses between silicon substrate 12 and nitride layer 14. Nitride layer 14 functions as an etch stop during a subsequent planarization etching, as will be described. An oxide layer 16 is also applied over nitride layer 14. The purpose and function of pad oxide layer 10, nitride layer 14, and oxide layer 16 will be described more fully below.
Referring to FIG. 2, photoresist (not shown) is applied and patterned, and an etching step is performed using an appropriate sequence of etching chemicals as necessary to define isolation trenches 18 and mesa areas 20. When trenches 18 are relatively deep (one micron or greater), extended etching of silicon substrate 12 eventually removes the photoresist (not shown) over mesa areas 20. Since the chemical used to etch silicon substrate 12 is highly selective to oxide, oxide layer 16 functions as a secondary etch stop to prevent damage to nitride layer 14. Accordingly, oxide layer 16 is optional, and typically only used when etching deep trenches.
After etching the trench, oxide layer 16 is removed. A light oxidation is often also conducted at this point to remove etch damage from the trench bottoms and sidewalls.
Referring now to FIG. 3, a thick isolation oxide layer 22 is applied atop substrate 12. Isolation oxide layer 22 is sufficiently thick to fill isolation trenches 18 at least to the level of nitride layer 14. Isolation oxide layer 22 is subsequently etched (FIG. 4) using a planarization etching technique and using nitride layer 14 as an etch stop. Nitride layer 14 is subsequently removed (FIG. 5) leaving only pad oxide layer 10 atop mesa areas 20. Care must be used during the planarization etching to remove enough isolation layer oxide to expose underlying nitride layer 14, while insuring the height of the remaining oxide is at least as great as that of substrate 12. Otherwise, undesirable parasitic transistors are formed on the sidewalls of trenches.
Threshold voltage implanting and well implanting is then performed through pad oxide layer 10. Pad oxide layer 10 is typically damaged during the nitride etching and subsequent implanting, and cannot be subsequently used as a gate oxide. Therefore, it is removed. An etch performed to remove pad oxide layer 10 also removes a small portion of isolation oxide layer 22, as shown in FIG. 6. A gate oxide layer 26 (FIG. 7) and a polysilicon layer are applied, masked, and etched to form a FET gate 28. Finally, source and drain regions 24 are then formed, completing fabrication of the FET.
The foregoing method, while accomplishing the desired result, is somewhat inefficient. Particularly, the requirement of removing pad oxide layer 10 and then reapplying a gate oxide layer 26 results in unneeded repetition.